Patent · US Active

Three-dimensional memory device with partially discrete charge storage regions and method of making thereof

US9960180B1 · kind B1 · utility

26Cited by
49References
12Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMar 27, 2017
Grant dateMay 1, 2018
Priority date
Expiry dateMar 27, 2037

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10B43/50

Abstract

Memory openings can be formed through an alternating stack of insulating layers and sacrificial material layers. Memory stack structures including charge storage elements can be formed in the memory openings. Inter-level charge leakage in a three-dimensional memory device including a charge trapping layer can be minimized by employing a thin continuous charge trapping material layer within each memory opening. After removal of the sacrificial material layers and formation of backside recesses, discrete charge trapping material portions can be formed by selective growth of a charge trapping material from physically exposed surfaces of each thin continuous charge trapping material layer. The discrete charge trapping material portions can function as primary charge storage regions, and inter-level charge leakage can be minimized by the small thickness of the thin continuous charge trapping material layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.