Patent · US Active

Method for manufacturing TFT backplane and structure of TFT backplane

US9960195B2 · kind B2 · utility

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6Claims
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Key dates

Filing dateAug 15, 2014
Grant dateMay 1, 2018
Priority date
Expiry dateAug 15, 2034

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D86/60

Abstract

The present invention provides method for manufacturing a TFT backplane and a structure of a TFT backplane. The method includes (1) forming a gate terminal (2) and a first metal electrode M1 on a substrate (1); (2) sequentially forming a gate insulation layer (3), a semiconductor layer, and an etch stop layer on the gate terminal (2), the first metal electrode M1, and the substrate (1) in a successive manner and applying a photolithographic operation to form an island-like semiconductor layer (4) and an island-like etch stop layer (5); (3) applying a photolithographic operation to patternize the island-like etch stop layer (5) and the gate insulation layer (3) to form a plurality of etch stop layer vias (51) and a gate insulation layer via (31); (4) forming source/drain terminals (6) and a second metal electrode M2; (5) forming a passivation protection layer (7); (6) forming a planarization layer (8); (7) forming a pixel electrode layer (9); (8) forming a pixel definition layer (10); and (9) forming a spacer pillar (11).

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.