Reduced size split gate non-volatile flash memory cell and method of making same
US9960242B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 24, 2017 |
| Grant date | May 1, 2018 |
| Priority date | — |
| Expiry date | Mar 24, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A reduced size non-volatile memory cell array is achieved by forming first trenches in an insulation layer in the row direction, filling the first trenches with insulation material, forming second trenches in the insulation layer in the column direction, forming the STI isolation material in the second trenches, and forming the source regions through the first trenches. Alternately, the STI isolation regions can be made continuous, and the source diffusion implant has sufficient energy to form continuous source line diffusions that each extend across the active regions and under the STI isolation regions. This allows control gates of adjacent memory cell pairs to be formed closer together.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.