Temporal change in data-crossing clock phase difference to resolve meta-stability in a clock and data recovery circuit
US9960902B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2016 |
| Grant date | May 1, 2018 |
| Priority date | — |
| Expiry date | Dec 15, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An example method of clock and data recovery in a receiver includes generating data samples and crossing samples of a received signal based on a data clock signal and a crossing clock signal, respectively, which are derived from a sampling clock signal; adjusting a phase of the sampling clock signal using a clock and data recovery (CDR) circuit based on the data samples and the crossing samples; adjusting relative phase between the data clock signal and the crossing clock signal from a first phase difference to a second phase difference that is less than ninety degrees; and reverting the relative phase between the data clock signal and the crossing clock signal to the first phase difference after a threshold time period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.