Apparatus and method for flushing dirty cache lines based on cache activity levels
US9965023B2 · kind B2 · utility
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4References
25Claims
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Key dates
| Filing date | Sep 13, 2016 |
| Grant date | May 8, 2018 |
| Priority date | — |
| Expiry date | Oct 18, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method performed by a multi-core processor is described. The method includes, while a core is executing program code, reading a dirty cache line from the core's last level cache and sending the dirty cache line from the core for storage external from the core, where, the dirty cache line has not been evicted from the cache nor requested by another core or processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.