Computer processor employing bypass network using result tags for routing result operands
US9965274B2 · kind B2 · utility
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10Claims
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Key dates
| Filing date | Oct 15, 2014 |
| Grant date | May 8, 2018 |
| Priority date | — |
| Expiry date | Apr 18, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer processor is provided with a plurality of functional units that performs operations specified by the at least one instruction over the multiple machine cycles, wherein the operations produce result operands. The processor also includes circuitry that generates result tags dynamically according to the number of operations that produce result operands in a given machine cycle. A bypass network is configured to provide data paths for transfer of operand data between the plurality of functional units according to the result tags.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.