Memory device including page buffer and method of arranging page buffer having cache latches
US9965388B2 · kind B2 · utility
5Cited by
1References
16Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 4, 2017 |
| Grant date | May 8, 2018 |
| Priority date | — |
| Expiry date | Jan 4, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5643
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a memory cell array, a plurality of bit lines, and a plurality of page buffers including a plurality of cache latches, exchanging data with the memory cell array through the plurality of bit lines, wherein the plurality of cache latches are arranged in a column direction in parallel with the plurality of bit lines and a row direction perpendicular to the plurality of bit lines, and have a two-dimensional arrangement of M stages in the column direction, where M is a positive integer not corresponding to 2L and L is zero or a natural number.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.