Multiple-queue integer coalescing mapping algorithm with shared based time
US9965419B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 4, 2016 |
| Grant date | May 8, 2018 |
| Priority date | — |
| Expiry date | Aug 27, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A mapping technique sets coalescing latency values for computing systems that use multiple data queues having a shared base timer. A computing system having at least one receive queue and at least one transmit queue receives user-provided coalescing latency values for the respective queues, and converts these user-provided latencies to coalescing latency hardware register values as well as a base timer register value for the shared base timer. The hardware register values for the coalescing latencies together with the shared base timer register value determine the coalescing latencies for the respective queues. This mapping technique allows a user to conveniently set coalescing latencies for multi-queue processing systems while shielding the user settings from hardware complexity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.