Systems and methods of pipelined output latching involving synchronous memory arrays
US9966118B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2016 |
| Grant date | May 8, 2018 |
| Priority date | — |
| Expiry date | Dec 13, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2272
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods of synchronous memories and synchronous memory operation are disclosed. According to one illustrative implementation, a memory device is disclosed comprising memory circuitry having a memory output, the memory circuitry including a sense amplifier having a first output and a second output, a first data path coupled to the first output of the sense amplifier, the first data path including 2 latches/registers, and a second data path coupled to the second output of the sense amplifier, the second data path including a plurality latches/registers. In further implementations, various control circuitry, connections and control signals may be utilized to operate the latches/registers in the first and second data paths according to specified configurations, control, modes, latency and/or timing domain information, to achieve, for example, pipelined output latching and/or double data rate output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.