Controller and control method for dynamic random access memory
US9966129B1 · kind B1 · utility
2Cited by
3References
20Claims
0Family size
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Key dates
| Filing date | May 19, 2017 |
| Grant date | May 8, 2018 |
| Priority date | — |
| Expiry date | May 19, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10159
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A schedule for refreshing a dynamic random access memory (DRAM). Access commands for a DRAM are queued in a command queue. First-rank bank-refresh time points and second-rank bank-refresh time points are alternately provided within a refresh inspection interval for the microcontroller to alternately refresh a first rank and a second rank of the DRAM bank-by-bank based on the content contained in the command queue.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.