Instruction and logic for support of code modification
US9971599B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 8, 2017 |
| Grant date | May 15, 2018 |
| Priority date | — |
| Expiry date | May 8, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/452
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes support for executing binary-translated code including code modifications. The processor includes a processor core that includes a cache to store translation indicators from a physical map, each translation indicator to indicate whether a corresponding memory location includes translated code to be protected. The processor core also includes logic to execute a translated instruction. The translated instruction is translated from an instruction stored in a memory location. The processor core further includes logic to set a translation indicator in the cache corresponding to the memory location to indicate that it includes translated code to be protected. The processor core also includes logic to request senior store buffer drains of other processor cores of the processor based upon the execution of the translated instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.