Apparatus and method for programming ECC-enabled NAND flash memory
US9971647B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 31, 2014 |
| Grant date | May 15, 2018 |
| Priority date | — |
| Expiry date | Feb 21, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The NAND flash memory array in a memory device may be programmed using a cache program execute technique for fast performance. The memory device includes a page buffer, which may be implemented as a cache register and a data register. Program data may be loaded to the cache register, where it may be processed by an error correction code (“ECC”) circuit. Thereafter, the ECC processed data in the cache register may be replicated to the data register and used to program the NAND flash memory array. Advantageously, immediately after the ECC processed data in the cache register is replicated to the data register, the cache register may be made available for other operations. Of particular benefit is that a second page of program data may be loaded into the cache register and ECC processed while the first page of program data is being programmed into the NAND flash memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.