Method and apparatus for multiple memory shared collar architecture
US9971663B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2015 |
| Grant date | May 15, 2018 |
| Priority date | — |
| Expiry date | Jun 25, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for reducing memory built-in self-test (MBIST) area by optimizing the number of interfaces required for testing a given set of memories is provided. The method begins when memories of a same configuration are grouped together. One memory is then selected from each of the groups. MBIST insertion is then performed for a selected group of memories, and the selected group of memories contains memories of different configurations. Control logic is used to select each group of memories separately. The memory group under test may also be selected using programmable user bits. An apparatus is also provided. The apparatus includes: a controller, at least one memory interface in communication with the controller, at least one control logic cloud in communication with the at least one memory interface; and at least one bit bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.