Method and apparatus for performing register retiming in the presence of false path timing analysis exceptions
US9971858B1 · kind B1 · utility
3Cited by
37References
22Claims
0Family size
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Key dates
| Filing date | Feb 20, 2015 |
| Grant date | May 15, 2018 |
| Priority date | — |
| Expiry date | Jan 28, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for designing a system on a target device includes identifying a timing exception for a portion of a signal path. An area on the target device that includes components affected by the timing exception. Register retiming is performed where pipeline registers are added at boundaries of the area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.