Patent · US Active

Selective boundary overlay insertion for hierarchical circuit design

US9971861B2 · kind B2 · utility

2Cited by

12References

14Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Erwin Behnen · Holzgerlingen, DE
Michael S. Gray · Saint Albans, US
Matthew T. Guzowski · South Burlington, US
David Wolpert · Poughkeepsie, US

Key dates

Filing date	Feb 10, 2016
Grant date	May 15, 2018
Priority date	—
Expiry date	Mar 19, 2036

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/333
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Aspects include techniques for selective boundary overlay insertion for hierarchical circuit design. A method may include determining, by a processing device, a block type of a child block. The method may further include electively inserting, by the processing device, at least one of an instantiated boundary overlay and a merged boundary overlay into the hierarchical circuit design based on the block type of the child block. The instantiated boundary overlay enables a parent block to pass a testing at an out-of-context level, and the merged boundary overlay enables the parent block to continue to pass the testing when the child block is inserted into the parent block associated with the child block.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.