Row and column decoders comprising fully depleted silicon-on-insulator transistors for use in flash memory systems
US9972395B2 · kind B2 · utility
3Cited by
8References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 5, 2015 |
| Grant date | May 15, 2018 |
| Priority date | — |
| Expiry date | Oct 5, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a flash memory system wherein one or more circuit blocks utilize fully depleted silicon-on-insulator transistor design to minimize leakage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.