Method of fabricating a gate cap layer
US9972498B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2016 |
| Grant date | May 15, 2018 |
| Priority date | — |
| Expiry date | Jul 30, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28114
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a gate cap layer includes providing a substrate with an interlayer dielectric disposed thereon, wherein a recess is disposed in the interlayer dielectric and a metal gate fills in a lower portion of the recess. Later, a cap material layer is formed to cover the interlayer dielectric and fill in an upper portion of the recess. After that, a first sacrifice layer and a second sacrifice layer are formed in sequence to cover the cap material layer. The first sacrifice layer has a composition different from a composition of the cap material layer. The second sacrifice layer has a composition the same as the composition of the cap material layer. Next, a chemical mechanical polishing process is preformed to remove the second sacrifice layer, the first sacrifice layer and the cap material layer above a top surface of the interlayer dielectric.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.