Logic cell structure and method
US9972571B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 11, 2017 |
| Grant date | May 15, 2018 |
| Priority date | — |
| Expiry date | Apr 11, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/975
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The semiconductor structure includes a semiconductor substrate; field-effect devices disposed on the semiconductor substrate, wherein the field-effect devices include gates with elongated shape oriented in a first direction; a first metal layer disposed over the gates; a second metal layer disposed over the first metal layer; and a third metal layer disposed over the second metal layer. The first metal layer includes a plurality of first metal lines oriented in a second direction perpendicular to the first direction. The second metal layer includes a plurality of second metal lines oriented in the first direction. The third metal layer includes a plurality of third metal lines oriented in the second direction. The first metal lines have a first thickness, the second metal lines have a second thickness, the third metal lines have a third thickness, and the second thickness is less than the first thickness and the third thickness.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.