Semiconductor package and method for fabricating the same
US9972580B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 8, 2016 |
| Grant date | May 15, 2018 |
| Priority date | — |
| Expiry date | Nov 8, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/37001
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a stack structure, a mold layer disposed on at least one sidewall of the stack structure, a redistribution line electrically connected to the stack structure, and an external terminal electrically connected to the redistribution line. The stack structure includes a semiconductor chip having an active surface and a non-active surface opposite to the active surface. A dummy substrate is disposed on the non-active surface of the semiconductor chip. An adhesive layer is disposed between the dummy substrate and the semiconductor chip. The mold layer includes a top surface adjacent to the redistribution line and a bottom surface opposite to the top surface. The dummy substrate is exposed through the bottom surface of the mold layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.