Method for fabricating fan-out wafer level package and fan-out wafer level package fabricated thereby
US9972605B2 · kind B2 · utility
4Cited by
4References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 4, 2017 |
| Grant date | May 15, 2018 |
| Priority date | — |
| Expiry date | Apr 4, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06544
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a fan-out wafer level package includes disposing a first semiconductor chip on a dummy substrate, forming a mold substrate on the first semiconductor chip and the dummy substrate, removing the dummy substrate to expose the first semiconductor chip, disposing a second semiconductor chip on the exposed first semiconductor chip, forming an insulating layer on the second semiconductor chip, the first semiconductor chip, and the mold substrate, and forming a plurality of redistribution lines that electrically connects the first semiconductor chip and the second semiconductor chip through the insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.