Method for manufacturing a CMOS device and associated device

US9972622B2 · kind B2 · utility

Assignee

• IMEC VZW · BE

Inventors

• Liesbeth Witters · Linden, BE
• Anabela Veloso · Leuven, BE

Key dates

• Filing date: May 12, 2016
• Grant date: May 15, 2018
• Expiry date: Jun 15, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/853

Abstract

A method for manufacturing a CMOS device includes providing a semiconductor base layer epitaxially growing a germanium layer on the semiconductor base layer, the germanium layer having thickness above a critical thickness such that an upper portion of the germanium layer is strain relaxed. The method also includes performing an anneal step, thinning the germanium layer and patterning the germanium layer into fin structures or into vertical wire structures. The method further includes laterally embedding the fin structures or vertical wire structures in a dielectric layer and providing a masking layer covering the first region, leaving the second region exposed. The method yet further includes selectively removing the fin structure or vertical wire structure in the second region up until the main upper surface, resulting in a trench and growing a protrusion in the trench by epitaxially growing one or more semiconductor layers in the trench.