Double heterojunction field effect transistor with polarization compensated layer

US9972708B2 · kind B2 · utility

Assignee

• Qorvo US, Inc. · US

Inventors

• Jinqiao Xie · Allen, US
• Edward A. Beam, III · Dallas, US
• Xing Gu · Allen, US

Key dates

• Filing date: Mar 24, 2017
• Grant date: May 15, 2018
• Expiry date: Mar 24, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/149

Abstract

A semiconductor device includes a substrate, a relaxation layer, a channel layer, a polarization compensation layer, and a barrier layer. The relaxation layer is over the substrate and configured to reduce a total strain of the semiconductor device. The channel layer is over the relaxation layer. The polarization compensation layer is between the relaxation layer and the channel layer and configured to reduce a polarization between the relaxation layer and the channel layer. The barrier layer is over the relaxation layer and configured to polarize a junction between the barrier layer and the channel layer to induce a two-dimensional electron gas in the channel layer.