Block memory layout and architecture for programmable logic IC, and method of operating same
US9973194B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2016 |
| Grant date | May 15, 2018 |
| Priority date | — |
| Expiry date | Aug 18, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/025
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit comprising programmable/configurable logic circuitry including a plurality of logic tiles, arranged in an array, wherein each logic tile includes logic circuitry and I/O connected in an interconnect network via multiplexers. A first logic tile includes (i) a first portion of a perimeter which forms at least a portion of the periphery of the programmable/configurable logic circuitry and (ii) a second portion of a perimeter which is interior to such circuitry's periphery, wherein memory I/O is disposed on the second portion of the perimeter of the first logic tile. A second logic tile includes a second portion of a perimeter which is interior to the programmable/configurable logic circuitry's periphery and opposes the first logic tile's perimeter. Memory array(s), located between the second portions of the perimeters of the first and second logic tiles, is/are coupled to memory I/O of at least the first logic tile.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.