Systems and methods for wafer-level loopback test

US9977078B2 · kind B2 · utility

Assignee

• QUALCOMM Incorporated · US

Inventors

• Alvin Leng Sun Loke · Fort Collins, US
• Thomas Clark Bryan · Carlsbad, US
• Reza Jalilizeinali · San Diego, US
• Tin Tin Wee · Singapore, SG
• Stephen Knol · San Diego, US
• LuVerne Ray Peterson · San Diego, US

Key dates

• Filing date: Jul 23, 2014
• Grant date: May 22, 2018
• Expiry date: Mar 27, 2036

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318513
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

Circuits and methods for loopback testing are provided. A die incorporates a receiver (RX) to each transmitter (TX) as well as a TX to each RX. This architecture is applied to each bit so, e.g., a die that transmits or receives 32 data bits during operation would have 32 transceivers (one for each bit). Focusing on one of the transceivers, a loopback architecture includes a TX data path and an RX data path that are coupled to each other through an external contact, such as a via at the transceiver. The die further includes a transmit clock tree feeding the TX data path and a receive clock tree feeding the RX data path. The transmit clock tree feeds the receive clock tree through a conductive clock node that is exposed on a surface of the die. Some systems further include a variable delay in the clock path.