Reconfigurable parallel execution and load-store slice processor

US9977678B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Lee Evan Eisen · Round Rock, US
• Hung Q. Le · Austin, US
• Jentje Leenstra · Nagold, DE
• Jose E. Moreira · Dobbs Ferry, US
• Bruce Joseph Ronchetti · Austin, US
• Brian W. Thompto · Austin, US
• Albert J. Van Norstrand, Jr. · Round Rock, US

Key dates

• Filing date: Jan 12, 2015
• Grant date: May 22, 2018
• Expiry date: Feb 24, 2036

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02D10/00
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A processor core having multiple parallel instruction execution slices and coupled to multiple dispatch queues by a dispatch routing network provides flexible and efficient use of internal resources. The configuration of the execution slices is selectable so that capabilities of the processor core can be adjusted according to execution requirements for the instruction streams. Two or more execution slices can be combined as super-slices to handle wider data, wider operands and/or vector operations, according to one or more mode control signal that also serves as a configuration control signal. The mode control signal is also used to partition clusters of the execution slices within the processor core according to whether single-threaded or multi-threaded operation is selected, and additionally according to a number of hardware threads that are active.