Patent · US Active

Method and apparatus for calculating delay timing values for an integrated circuit design

US9977849B2 · kind B2 · utility

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0References

16Claims

0Family size

Assignee

NXP USA, Inc. · US

Inventors

Sergey Sofer · Rishon LeZion, IL
Asher Berkovitz · Kiryat Ono, IL
Michael Priel · Netanya, IL

Key dates

Filing date	Jan 9, 2013
Grant date	May 22, 2018
Priority date	—
Expiry date	Jan 9, 2033

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/398
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method and apparatus for calculating delay timing values for at least a part of an integrated circuit design. The method comprises applying a first Negative/Positive Bias Temperature Instability compensation margin to delay values for elements within the at least part of the IC design, identifying at least one lower-rate switching element within the at least part of the IC design, and applying at least one further, increased N/PBTI compensation margin to the delay value(s) for the at least one identified lower-rate switching element.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.