No miss cache structure for real-time image transformations with data compression
US9978118B1 · kind B1 · utility
46Cited by
13References
24Claims
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Key dates
| Filing date | Jan 25, 2017 |
| Grant date | May 22, 2018 |
| Priority date | — |
| Expiry date | Jan 25, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are disclosed herein for providing improved cache structures and methods that are optimally sized to support a predetermined range of late stage adjustments and in which image data is intelligently read out of DRAM and cached in such a way as to eliminate re-fetching of input image data from DRAM and minimize DRAM bandwidth and power. The systems and methods can also be adapted to work with compressed image data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.