Semiconductor substrate and semiconductor package structure having the same
US9978705B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2016 |
| Grant date | May 22, 2018 |
| Priority date | — |
| Expiry date | Jul 28, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10674
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package structure includes a substrate, a semiconductor chip, and a solder material. The substrate includes an insulating layer, a conductive circuit layer, and a conductive bump. The conductive circuit layer is recessed from a top surface of the insulating layer. The conductive circuit layer includes a pad, and a side surface of the pad extends along a side surface of the insulating layer. The conductive bump is disposed on the pad. A side surface of the conductive bump, a top surface of the pad and the side surface of the insulating layer together define an accommodating space. A solder material electrically connects the conductive bump and the semiconductor chip. A portion of the solder material is disposed in the accommodating space.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.