Method for self-aligned solder reflow bonding and devices obtained thereof
US9978710B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 20, 2016 |
| Grant date | May 22, 2018 |
| Priority date | — |
| Expiry date | Dec 20, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/01074
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for producing a stack of semiconductor devices and the stacked device obtained thereof are disclosed. In one aspect, the method includes providing a first semiconductor device comprising a dielectric layer with a hole, the hole lined with a metal layer and partially filled with solder material. The method also includes providing a second semiconductor device with a compliant layer having a metal protrusion through the compliant layer, the protrusion capped with a capping layer. The method further includes mounting the devices by landing the metal protrusion in the hole, where the compliant layer is spaced from the dielectric layer. The method includes thereafter reflowing the solder material, thereby bonding the devices such that the compliant layer is contacting the dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.