Voltage balanced stacked clamp
US9978743B1 · kind B1 · utility
2Cited by
4References
1Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2017 |
| Grant date | May 22, 2018 |
| Priority date | — |
| Expiry date | Sep 25, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0948
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention provide methods for balancing voltages during voltage division. More specifically, circuit performance is enhanced (i) balancing out the voltage drops across two field effect transistors (FETs); (ii) powering inverters through a voltage divider containing two voltage input pins during normal operation of the circuit; and (iii) powering inverters through a FET during electrostatic discharge.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.