Method for producing a high-voltage transistor with reduced footprint, and corresponding integrated circuit
US9978847B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2017 |
| Grant date | May 22, 2018 |
| Priority date | — |
| Expiry date | Mar 9, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/518
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated MOS transistor is formed in a substrate. The transistor includes a gate region buried in a trench of the substrate. The gate region is surrounded by a dielectric region covering internal walls of the trench. A source region and drain region are situated in the substrate on opposite sides of the trench. The dielectric region includes an upper dielectric zone situated at least partially between an upper part of the gate region and the source and drain regions. The dielectric region further includes a lower dielectric zone that is less thick than the upper dielectric zone and is situated between a lower part of the gate region and the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.