Patent · US Active

Built-in self test controller for a random number generator core

US9983262B1 · kind B1 · utility

4Cited by
0References
20Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJun 30, 2016
Grant dateMay 29, 2018
Priority date—
Expiry dateDec 10, 2036

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG01R31/318525
  • WIPO fieldMeasurement
  • WIPO sectorInstruments

Abstract

A device includes one or more random number generator (RNG) cores (e.g., true random number generator cores) and a built-in self-test controller (BIST) configured to perform various fault tests on each RNG core. The tests include a stuck-at-1 fault test, a stuck-at-0 fault test, and a transition delay fault test. For those RNG cores that have multiple ring oscillators, each individual ring oscillator is fault tested by the BIST controller. For those RNG cores that have a multi-tap inverter chain configuration, the individual taps may be tested by the BIST controller. The RNG core also may comprise a bi-stable cell which can be tested by the BIST controller as well.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.