Fabricating contacts of a CMOS structure
US9984929B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 2017 |
| Grant date | May 29, 2018 |
| Priority date | — |
| Expiry date | Nov 1, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention relates to a method comprising providing a substrate with a channel layer, forming a gate stack structure on the channel layer and forming a raised source and a raised drain on the channel layer. The method further comprises depositing in a non-conformal way an oxide layer above the gate stack structure, the raised source and the raised drain. A first void above the raised source and a second void above the raised drain gate are created adjacent to vertical edges of the gate stack structure. The method further comprises etching the oxide layer for a predefined etching time, thereby removing the oxide layer above the raised source and the raised drain, while keeping it at least partly on the channel layer. Contacts are formed to the raised source and the raised drain. The invention also concerns a corresponding computer program product.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.