CMOS image sensor with dual damascene grid design having absorption enhancement structure
US9985072B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2017 |
| Grant date | May 29, 2018 |
| Priority date | — |
| Expiry date | Mar 27, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/809
Abstract
The present disclosure relates to an image sensor integrated chip having a grid structure that reduces crosstalk between pixel regions of an image sensor chip. In some embodiments, the integrated chip has an image sensing element arranged within a substrate. An absorption enhancement structure is disposed along the back-side of the substrate. A grid structure is arranged over the absorption enhancement structure. The grid structure defines an opening arranged over the image sensing element and extends from over the absorption enhancement structure to a location within the absorption enhancement structure. By having the grid structure extend into the absorption enhancement structure, the grid structure is able to reduce crosstalk between adjacent image sensing elements by blocking radiation reflected off of non-planar surfaces of the absorption enhancement structure from traveling to an adjacent pixel region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.