Semiconductor process
US9985110B2 · kind B2 · utility
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10References
9Claims
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Key dates
| Filing date | Jul 21, 2017 |
| Grant date | May 29, 2018 |
| Priority date | — |
| Expiry date | Jul 21, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76855
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor process is described. A silicon-phosphorus (SiP) epitaxial layer is formed serving as a source/drain (S/D) region. A crystalline metal silicide layer is formed directly on the SiP epitaxial layer and thus prevents oxidation of the SiP epitaxial layer. A contact plug is formed over the crystalline metal silicide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.