Programmable delay circuit including hybrid fin field effect transistors (finFETs)
US9985616B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2017 |
| Grant date | May 29, 2018 |
| Priority date | — |
| Expiry date | Jan 3, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00221
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Embodiments relate to programmable delay circuit. An aspect includes a first stage comprising a first hybrid fin field effect transistor (finFET) comprising a first gate corresponding to a first control FET, and a second gate corresponding to a first default FET, and a first plurality of fins, wherein the first gate and the second gate of the first stage each partially control a first shared fin of the first plurality of fins. Another aspect includes a second stage connected in series with the first stage, the second stage comprising a second hybrid finFET comprising a first gate corresponding to a second control FET, and a second gate corresponding to a second default FET, and a second plurality of fins, wherein the first gate and the second gate of the second stage each partially control a second shared fin of the second plurality of fins.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.