Electronic device having fault monitoring for a memory and associated methods
US9990245B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 25, 2015 |
| Grant date | Jun 5, 2018 |
| Priority date | — |
| Expiry date | Mar 18, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/42
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic device includes a memory having memory locations being subject to transient faults and permanent faults, and a fault detection circuit coupled to the memory. The fault detection circuit is configured to read the memory locations at a first time, and determine a first fault count and fault map signature including the transient and permanent faults at the first time based upon reading the plurality of memory locations, and to store the first fault count and fault map signature. The fault detection circuit is configured to read the memory locations at a second time and determine a second fault count and fault map signature including the transient and permanent faults at the second time based upon reading the memory locations, and compare the stored first fault count and fault map signature with the second fault count and fault map signature to determine a permanent fault count.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.