Om Ranjan
9Patents
1h-index
7Co-inventors
36Inventor score
Filing activity: Mar 18, 2014 → Jun 7, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US11055173B2 | Redundant storage of error correction code (ECC) checkbits for validating proper operation of a static random access memory (SRAM) | Physics | 1 | Active |
| US11822934B2 | Processing system, related integrated circuit, device and method | Electricity | 0 | Active |
| US11048525B2 | Processing system, related integrated circuit, device and method | Electricity | 0 | Active |
| US10528422B2 | Redundant storage of error correction code (ECC) checkbits for validating proper operation of a static random access memory (SRAM) | Physics | 0 | Active |
| US11436162B2 | Functional safety method, corresponding system-on-chip, device and vehicle | Physics | 0 | Active |
| US10379937B2 | Memory architecture including response manager for error correction circuit | Electricity | 0 | Active |
| US10860415B2 | Memory architecture including response manager for error correction circuit | Electricity | 0 | Active |
| US9990245B2 | Electronic device having fault monitoring for a memory and associated methods | Physics | 0 | Active |
| US9558052B2 | Safe scheduler for finite state deterministic application | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.