Memory system
US9990246B2 · kind B2 · utility
5Cited by
21References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2013 |
| Grant date | Jun 5, 2018 |
| Priority date | — |
| Expiry date | Oct 1, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided is a device for use in a memory module coupled to a host memory controller over a bus, comprising memory module control logic to generate a request signal to a host memory controller having a pulse width greater than or equal to a minimum pulse width, wherein the minimum pulse width comprises a number of clock cycles needed to guarantee that the host memory controller detects the request signal, and wherein the pulse width of the request signal indicates at least one function in addition to the request signal to the host memory controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.