Apparatus and method for memory-hierarchy aware producer-consumer instruction
US9990287B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2011 |
| Grant date | Jun 5, 2018 |
| Priority date | — |
| Expiry date | Apr 3, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G5/006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method are described for efficiently transferring data from a core of a central processing unit (CPU) to a graphics processing unit (GPU). For example, one embodiment of a method comprises: writing data to a buffer within the core of the CPU until a designated amount of data has been written; upon detecting that the designated amount of data has been written, responsively generating an eviction cycle, the eviction cycle causing the data to be transferred from the buffer to a cache accessible by both the core and the GPU; setting an indication to indicate to the GPU that data is available in the cache; and upon the GPU detecting the indication, providing the data to the GPU from the cache upon receipt of a read signal from the GPU.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.