Energy-efficient dynamic dram cache sizing via selective refresh of a cache in a dram
US9990293B2 · kind B2 · utility
1Cited by
8References
24Claims
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Key dates
| Filing date | Aug 12, 2014 |
| Grant date | Jun 5, 2018 |
| Priority date | — |
| Expiry date | Apr 7, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques described herein generally include methods and systems related to improving energy efficiency in a chip multiprocessor by reducing the energy consumption of a DRAM cache for such a multi-chip processor. Methods of varying refresh interval may be used to improve the energy efficiency of such a DRAM cache. Specifically, a per-set refresh interval based on retention time of memory blocks in the set may be determined, and, starting from the leakiest memory block, memory blocks stored in the DRAM cache that are associated with data also stored in a lower level of cache are not refreshed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.