Memory system and operation method of the same
US9990312B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 6, 2016 |
| Grant date | Jun 5, 2018 |
| Priority date | — |
| Expiry date | Feb 8, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/76
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes: a plurality of memory devices, one of which includes an unrepaired defective memory cell; a control bus that is shared by the plurality of the memory devices; a plurality of data buses assigned to each of the plurality of the memory devices; and a memory controller that communicates with the plurality of the memory devices through the control bus and the plurality of the data buses, a control latency of the memory device including unrepaired defective memory cells is set differently from a control latency of the other memory devices, where the control latency is used for recognizing control signals of the control bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.