Instructions and logic to interrupt and resume paging in a secure enclave page cache

US9990314B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Carlos V. Rozas · Portland, US
• Ilya Alexandrovich · Haifa, IL
• Gilbert Neiger · Hillsboro, US
• Francis X. McKeen · Portland, US
• Ittai Anati · Ramat HaSharon, IL
• Vedvyas Shanbhogue · Austin, US
• Shay Gueron · Haifa, IL

Key dates

• Filing date: Jun 2, 2017
• Grant date: Jun 5, 2018
• Expiry date: Jun 2, 2037

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2212/62
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Instructions and logic interrupt and resume paging in secure enclaves. Embodiments include instructions, specify page addresses allocated to a secure enclave, the instructions are decoded for execution by a processor. The processor includes an enclave page cache to store secure data in a first cache line and in a last cache line for a page corresponding to the page address. A page state is read from the first or last cache line for the page when an entry in an enclave page cache mapping for the page indicates only a partial page is stored in the enclave page cache. The entry for a partial page may be set, and a new page state may be recorded in the first cache line when writing-back, or in the last cache line when loading the page when the instruction's execution is being interrupted. Thus the writing-back, or loading can be resumed.