Patent · US Active

Memory with margin current addition and related methods

US9991000B2 · kind B2 · utility

3Cited by

6References

20Claims

0Family size

Assignee

STMicroelectronics SA

Inventors

Emanuela Calvetti · Merate, IT
Marcella Carissimi · Dalmine, IT
Marco Pasotti · Pavia, IT

Key dates

Filing date	Mar 31, 2017
Grant date	Jun 5, 2018
Priority date	—
Expiry date	Mar 31, 2037

Classification

Technology area (CPC G)Physics
CPC primaryG11C2013/0066
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In accordance with an embodiment, a circuit includes a sense amplifier circuit configured to sense a difference between a first current based on a direct memory bit and a second current based on a complementary memory bit. The direct memory bit is coupled to a first input of the sense amplifier circuit, and the complementary memory bit is coupled to a second input of the sense amplifier circuit. A controller is configured to, during a sense operation, selectively add a first margin current to the first current, and during the sense operation, selectively add a second margin current to the second current.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.