Doped protection layer for contact formation
US9991123B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 2, 2017 |
| Grant date | Jun 5, 2018 |
| Priority date | — |
| Expiry date | May 2, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device is provided. The semiconductor device includes a semiconductor substrate including a first doped region and a second doped region and a gate stack on the semiconductor substrate. The semiconductor device also includes a main spacer layer on a sidewall of the gate stack and a protection layer between the main spacer layer and the semiconductor substrate. The protection layer is doped with a quadrivalent element. The semiconductor device further includes an insulating layer formed over the semiconductor substrate and the gate stack and a contact formed in the insulating layer. The contact includes a first portion contacting the first doped region, and the contact includes a second portion contacting the second doped region. The first portion extends deeper into the semiconductor substrate than the second portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.