Patent · US Active

Semiconductor memory device and semiconductor memory array comprising the same

US9991266B2 · kind B2 · utility

0Cited by
3References
20Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJun 13, 2016
Grant dateJun 5, 2018
Priority date—
Expiry dateJun 13, 2036

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D86/60
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

A semiconductor array, the semiconductor memory array includes bit lines, word lines and memory cells. The bit lines are arranged in parallel in a first direction, and the word lines are arranged in parallel in a second direction which is different from the first direction. The memory cells are arranged in an array and electrically connected to corresponding bit lines and word lines respectively, and any two memory cells adjacent to each other share a same oxide semiconductor layer as a channel layer. The present invention also relates to a semiconductor memory device including two memory cells sharing a same oxide semiconductor layer as a channel layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.