Trench FET with ruggedness enhancement regions

US9991377B2 · kind B2 · utility

Assignee

• Infineon Technologies Americas Corp. · US

Inventors

• Ashita Mirchandani · El Segundo, US
• Timothy Henson · Torrance, US
• Ling Ma · Huizhou, CN
• Niraj Ranjan · El Segundo, US

Key dates

• Filing date: Mar 11, 2013
• Grant date: Jun 5, 2018
• Expiry date: Mar 11, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/256

Abstract

According to an exemplary implementation, a field-effect transistor (FET) includes first and second gate trenches extending to a drift region of a first conductivity type. The FET also includes a base region of a second conductivity type that is situated between the first and second gate trenches. A ruggedness enhancement region is situated between the first and second gate trenches, where the ruggedness enhancement region is configured to provide an enhanced avalanche current path from a drain region to the base region when the FET is in an avalanche condition. The enhanced avalanche current path is away from the first and second gate trenches. The ruggedness enhancement region can be of the second conductivity type that includes a higher dopant concentration than the base region. Furthermore, the ruggedness enhancement region can be extending below the first and second gate trenches.