Method and apparatus for proactive throttling for improved power transitions in a processor core
US9996127B2 · kind B2 · utility
2Cited by
2References
19Claims
0Family size
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Key dates
| Filing date | Mar 12, 2014 |
| Grant date | Jun 12, 2018 |
| Priority date | — |
| Expiry date | Dec 4, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor and method are described for performing proactive throttling of execution unit ports. For example, one embodiment of a processor core comprises: a plurality of execution unit ports within an execution stage of the processor core; a scheduler unit to schedule execution of a plurality of operations to the plurality of execution unit ports; and proactive throttling logic to limit acceleration of execution of the operations by the ports to an acceleration level which does not result in significant power supply droops.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.