Cache with compressed data and tag
US9996471B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2016 |
| Grant date | Jun 12, 2018 |
| Priority date | — |
| Expiry date | Jul 23, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/466
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Cache line data and metadata are compressed and stored in first and, optionally, second memory regions, the metadata including an address tag When the compressed data fit entirely within a primary block in the first memory region, both data and metadata are retrieved in a single memory access. Otherwise, overflow data is stored in an overflow block in the second memory region. The first and second memory regions may be located in the same row of a DRAM, for example, or in different regions of a DRAM and may be configured to enable standard DRAM components to be used. Compression and decompression logic circuits may be included in a memory controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.