Data transfer rate adjustment
US9996486B2 · kind B2 · utility
3Cited by
3References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2015 |
| Grant date | Jun 12, 2018 |
| Priority date | — |
| Expiry date | May 31, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4068
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A storage device may be configured to adjust a frequency of a clock signal. The clock signal may be associated with a data transfer rate of data to be communicated between a controller and a memory of the storage device. In some implementations, the frequency maybe adjusted responsive to at least one of a supply voltage provided to the storage device, a temperature of the storage device, or a physical characteristic of the storage device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.